다음의 잡 오프닝은 *진짜* 오프닝이며, 엔비디아의 SI (시그널 인테그리티) 부서에서 일하는 지인에게 받은 리스트입니다.

저는 VLSI나 SI쪽으로는 모릅니다. 요구사항을 정확히 읽어보시고 자신의 백그라운드와 맞는다고 생각하시면 [sonny앳nulltech쩜콤]으로 이메일 주십시요. 그 사람에게 포워딩하도록 하겠습니다.

만일 커버레터를 쓰실려면 저에게 쓰지 마시고 그 SI부서의 사람이 읽는다고 생각하고 쓰셔서 주십시요.

============================

시그널 인테그리티 매니저 #1229478

Managing one of 엔비디아’s centralized physical design signal integrity group, your group will be responsible for multiple projects from design to bring up. The team will work with logic, circuit designers, PCB and component engineers to ensure successful product development. An ideal candidate will have experience in SI modeling and correlation, SI team building, system bring up support, and customer co-development support.

RESPONSIBILITIES:
– You will be responsible for managing a team in the function of power delivery design, channel integrity design, system validation, system failure debug, and tier-1 customer support. The responsibilities of the team encompass interfaces like: PCI Express (PCIe) bus, Double Data Rate (DDR) memories, TMDS, Display Port, SATA, DAC, and USB. The work flow process will include development of advanced measurement strategies, model generations, system validation, and project ownership. Team manager is expected to institute design and validation procedures to ensure consistent product quality.
– Each of the group should have one or more of the specialized functions mentioned above base on work function. The idea is to bring focus into a particular segment of the task. The non-specialized work functions would be considered as secondary responsibilities.

MINIMUM REQUIREMENTS:
– BSEE, BSCE or equivalent international education or equivalent experience
– 10 years of experience in the field of signal integrity and high speed digital design in transmission line environments. At least 3 years of management experience preferred.
– Must have good knowledge with field solver and SI modeling theory. Hands on system bring up experience with different lab equipments is a plus. Customer technical support experience is also a plus. Some level of programming proficiencies are beneficial.
– Ability to manage multiple complex designs or bring up issues simultaneously is a must.

=============================

시그널 인테그리티 밸리데이션 엔지니어 #1245846

Working in 엔비디아’s centralized physical design engineering group, you will be responsible for system bring up to validate SI related characteristics. An ideal candidate will have exposure in system bring up environment where SI knowledge is essential in resolving issues.

PRIMARY RESPONSIBILITIES:
– You will be responsible for characterizing both power delivery and signal/channel integrity of all interfaces connected to 엔비디아 chips, including PCI Express (PCIe) bus, Double Data Rate (DDR) memories, TMDS, HyperTransport (HT), SATA, DAC, and USB the. Candidate will also be responsible for development of validation procedures and SI model correlation strategies.

SECONDARY RESPONSIBILITIES:
– Feedback 1st hand measurement data to development team to improve design efficiency.

MINIMUM REQUIREMENTS:
– BSEE, BSCE or equivalent international education or equivalent experience
– 2 years of experience in system bring up or system (board) development. Previous bring up or design experience in field of graphics, desktop, or server systems is a strong plus.
– Must be proficient with common SI equipments such as TDR, VNA, and high speed scope. Have working knowledge of signal integrity simulation tools such as HSPICE, HFSS, and SPEED2000 are strong plus. Some level of programming proficiencies are beneficial.
– Experience in SI test structure construction and validation is a plus.

========================

시니어 시그널 인테그리티 엔지니어 #1245845

Working in 엔비디아’s centralized physical design engineering group, you will be responsible for handling all the Power and Signal Integrity needs of 엔비디아’s projects from chip to package/board level. Work as part of a team with logic, circuit design, architects, package, PCB, and component engineers to ensure successful product development. An ideal candidate will have exposure in SI areas that involves high speed design, such as model generation, simulation, design constraint generation, system timing verification, etc. PI areas should involve large IC core power delivery, current profile generation, impedance profiling, and power delivery modeling from 실리콘 to PCB.

PRIMARY RESPONSIBILITIES:
– You will be responsible for the design both power delivery and channel integrity of all interfaces connected to the chip, including the PCI Express (PCIe) bus, Double Data Rate (DDR) memories, Display Port, HDMI, SATA, USB, and core VDD. The design process will include development of interface topologies, constraint generation, timing sign off, and silicon verification.

SECONDARY RESPONSIBILITIES:
– Contribute to design automation process with SI considerations. Help in stream line development process and increasing overall team efficiency.

MINIMUM REQUIREMENTS:
– BSEE, BSCE or equivalent international education or equivalent experience
– 5 years of experience in the field of signal integrity, power integrity, and high speed digital design where transmission line environments are common. Previous design experience in a field which may include networking, graphics or computer systems is a strong plus.
– Must be proficient with signal integrity simulation tools such as HSPICE, some form of 3D field solver (such as HFSS), and power integrity tools (such as Sigrity PowerSI). Some level of programming proficiency is beneficial.
– Experience correlating simulation results with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers is a plus.