Responsibility
• Design Verilog coding for ASIC design targeting power management applications including AC/DC and DC/DC converter control
• Design optimized digital blocks meeting functional, gate count and low power constraints
• Run simulations to verify the design using System Verilog
• Good but not required to have knowledge of digital backend design from synthesis, static timing and logic equivalent checking.
• Interface with P&R for digital hand-off and post layout verification
• Collaboration with analog engineers and test engineers on testability design and debugging
• Interface with P&R team for digital hand-off and post layout verification.
• Support physical silicon device evaluation where necessary
Qualification
• 1-5 years of direct experience in ASIC/IC design with good understanding of whole IC design flow from RTL coding and verification, synthesis, static timing analysis, logic equivalent checking to post-layout checking.
• Experience and knowledge in digital signal processing
• Knowledge on digital close loop control and low pass filter
• Experience in FPGA prototype, lab equipment and lab debug
• Fluent in either Verilog or VHDL RTL coding and ASIC design methodology
• Knowledge on power electronics and/or power management is a plus
• Good understanding of design constraints for synthesis, and static timing analysis (STA)
• Self-motivated and service minded.
• Ability to work both independently and part of a team
• Good team work and communications skills.
• Speaking Korean or Chinese plus
• 10% travelling to Korea
• H-visa /green card support