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않을까 싶습니다.Position Name
CV® Test Chip Design Engineer
Location
San Jose, California, USA;
Education
B.S/M.S in Electrical Engineering or related semiconductor design or process field.
Ph.D. in relevant field is desirable but not required.
Experience
M.S. with 0-2 years professional experience
B.S. with 2-4 years professional experience
Job Description
• Design, generate (automated layout) and verify (DRC, LVS, etc) specific
Characterization Vehicle® test chip layouts tuned to individual deep-submicron
client semiconductor processes to quantify process and design maturity. Both full-
reticle and scribe-line test structures are designed.
• Use PDF proprietary automated layout tools including layout generators, routers
and packaging tools to place and route CV® test chip structures.
• Use Industry Standard EDA tools for layout and verification including Cadence
Virtuoso, Magma Quartz, Magma Titan and Mentor Calibre DRC and LVS.
• Generate all collateral for CV test chip including layout and user-level
documentation, detailed design review documents and inspection documents for
client.
• Work directly with very experienced process engineers and designer to establish
customer-specific Design of Experiments for each CV test chip.
• May participate with client in detailed review of test chip including post-OPC
data review and pre mask-making reviews
• Depending on skill and background, may also design :
o Small to medium custom logic blocks (gates, counters, flip-flops, MUX)
that are incorporated into CV test chips.
o Small analog blocks (ring oscillators, matching circuitry, op-amps)
Required Skills and Experience
• Sound understanding of semiconductor manufacturing process and transistors
• Experience with semiconductor layout methods and layout tool suites (e.g.,
Cadence, Mentor, etc).
• Working knowledge of DRC and LVS tools and deck creation and application
• Basic knowledge of Unix scripting languages (e.g., perl, CSH, SH, Tcl, etc)
• Self-motivated and highly professional including some experience with customer
interactions
• Familiarity with interpreting and using Design Rule Manuals for deep sub-micron
semiconductor processes (both foundry and IDM)
• Experience using circuit modeling software (HSPICE, Spectre, etc)
Job Desirables
• Experience with Cadence Virtuoso and/or Cadence SKILL programming
language
• Basic knowledge of parametric test methods
• Experience with any part of Design for Manufacturability including design
modification, verification, algorithms for failure analysis, critical area analysis,
highly regular layout patterns, etc.
• Experience with high-level logic and timing verification of small sub-circuits
(including critical path analysis, LPE)
• Familiarity with semiconductor reticle-making practices (mask data prep, dummy
fill algorithms, basics of OPC, mask fracturing and biasing, etc)
• Experience with phase-shifting mask techniques or advanced Reticle
Enhancement Techniques
• Experience with Magma Titan or Magma Quartz DRC.